Analog Devices Clock Jitter Attenuator Optimizes JESD204B Serial Interface Functionality in Base Station Designs
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In base stations applications there are many serial JESD204B data converter channels that require their data frames to be aligned with an FPGA. The HMC7044 clock jitter attenuator simplifies JESD204B system design by generating source-synchronous and adjustable sample and frame alignment (SYSREF) clocks in a data converter system. The device features two phase-locked loops (PLLs) and overlapping, on-chip, voltage-controlled oscillators (VCOs). The first PLL locks a low-noise, local voltage-controlled clock oscillator (VCXO) to a relative noisy reference, while the second PLL multiplies the VCXO signal up to the VCO frequency with exceptionally little added noise. For cellular infrastructure JESD204B clock generation, wireless infrastructure, data converter clocking, microwave baseband cards and other high-speed communications applications, the architecture of the HMC7044 offers excellent frequency generation performance with low phase noise and integrated jitter.
HMC7044 Clock Jitter Attenuator Key Features
- JEDEC JESD204B support
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Ultra -low RMS jitter: 50 fs (12 KHz to 20 MHz, typical) - Noise floor: -162 dBc/Hz at 245.76 MHz
- Low phase noise: < -142 dBc/Hz at 800 kHz to 983.04 MHz output frequency
- Up to 14 device differential device clocks from PLL2
- External VCO input supports up to 5 GHz
- On-board regulators for excellent PSRR
Pricing and Availability
Product |
Sample |
Full Production |
Price Each per |
Packaging | ||||||||
HMC7044 | Now |
Q415 |
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68-lead
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or
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