JESD204B FPGA Debug Software Accelerates High-speed Design
Free, on-chip, 2-D statistical eyescan software enables fast in-system verification of high-speed data converter-to-FPGA signal integrity.
- Download the reference design: http://www.em.avnet.com/en-us/design/drc/Pages/Analog-Devices-Linux-JESD204B-Eyescan-Software.aspx
- View a video on JESD204B A/D converters, FPGAs and eyescan diagrams: http://videos.analog.com/video/products/analog-to-digital-converters/2534598195001/High-Speed-ADC-FMC-Development-Board-with-JESD204B/
- Learn more about Xilinx FPGAs: www.xilinx.com/jesd204
"The Analog Devices JESD204B Xilinx Transceiver Debug Tool provides
on-chip eyescanning that augments the test and measurement process by
statistically determining signal integrity inside the FPGA," said
ADI's reference design gathers data directly from the on-chip Rx margin analysis feature in the 7 series IBERT core and manages the data locally inside the FPGA or one of the ARM® dual-core Cortex™-A9 MPCore™ processors, displaying the data on an HDMI monitor or over Ethernet to a remote monitoring station. Typically, other scanning tools measure signals off-chip and require costly test and measurement equipment or transfer the data back over JTAG to be viewed on a host/development PC in the lab.
‘Live'
Alternative scanning tools typically measure high-speed data links by generating a pseudo-random bit stream (PRBS) that is checked for bit-level correctness in a closed development environment. This approach does not describe how well the design is performing or if it might be on the verge of failure. ADI's reference design measures link robustness using actual JESD204B serial data running to the FPGA. This use of "live" data enables signal fidelity to be monitored even after the design has been deployed in the field, which allows for real-time and predictive maintenance over the life of the product.
Pricing and Availability
Product | Availability | Price | ||||
JESD204B Xilinx Transceiver Debug Tool |
NOW | Free with ADI Converters | ||||
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